Sample
Design Task
| ADS 2006A
| ADS 2008
| Productivity
Improvements
|
| Zoom in schematic or layout |
- Select Zoom command
- Select area to zoom
|
One step:
Scroll mouse wheel to zoom in or out
|
 |
|
100% |
| Pan across schematic or layout |
- Select horizontal and vertical window scroll bar and drag across
- Select vertical window scroll bar and drag across
|
One step:
Click and hold right mouse button then drag OR press keyboard arrow keys |  |
|
100% |
| Copy and re-name/re-version top-level and dependent designs |
Individually re-name top-level and dependent designs |
One step:
Copy design using new Project View |
|
|
100%+ |
| Insert subnetwork |
- Open Library Browser
- Select subnetwork
- Place subnetwork
|
One step:
Drag subnetwork into Schematic or Layout from new Project View |
 |
|
200% |
| Transient simulation of 11,000 nodes† |
310 seconds |
8 seconds |
3800% |
| View multiple layers all at once |
Select one layer at a time to view |
| View all layers at once using new layer transparency |  |
|
100%+ |
| Insert trace and vias across 2 layers |
- Draw trace on layer 1
- Select via component
- Insert via
- Select layer 2
- Insert trace
|
Two steps:
| 1. |
Draw trace on layer 1 |
 |
| 2. |
Draw trace on layer 2 - via is automatically inserted |
|
150% |
| Insert bondwire |
- Create schematic
- Insert Bondwire component
- Insert bond wire shape component
|
One step:
Insert new JEDEC bondwire directly onto layout |  |
|
200% |
| Momentum simulation with ~10,000 unknowns |
23 minutes using single-core computer |
9 minutes, 59 seconds using quad-core computer†† |
130% |
| Identify Design Rule errors |
- Browse disk directories and select rules file
- Run Design Rule Check (DRC)
- Browse errors one at a time by clicking Next multiple times until desired error is displayed
|
Two steps:
| 1. |
Rules files are auto-loaded into project; Run Design Rule Check (DRC) |
 |
| 2. | All errors are displayed - select error and it is auto- zoomed in the layout |
|
100%+ |
| Access any help document |
3+ mouse clicks |
| One mouse click from ANY page |  |
|
200%+ |
| Find power at a circuit node |
- Insert Current Probe at node
- Write Data Display (DDS) expression for DC power
- Write another, complex DDS expression for AC power
- Display expression results
|
Two steps:
| 1. |
Place Power Probe at node |
 |
| 2. | Directly (no complex expressions are required) display DC and AC results |
|
200% |
| Find S-Parameters in each direction between every subnetwork in a 3-stage design |
1. through 4.
| | Create individual S-parameter Test Bench for each combination of subnetworks |
| 5. | Display and interpret results to find desired S-parameters. |
|
Two steps:
| 1. |
Create a single Test Bench, inserting the SP_Probe between each subnetwork |
 |
| 2. | Accurate results in each direction are automatically available for display. |
|
300% or more |
| Perform 2D/3D EM simulation on a layout |
1. through 6.
| | Export GDS file; import into EM tool; re-assign material information; setup geometry and ports; run simulation; import S-parameters into ADS – about 2 hours of additional work |
| 7. | Reconnect ports for verification |
|
Two steps:
| 1. |
Run EM simulation from ADS Layout |
 |
| 2. | Simulate Layout Component together with passives, then with active devices if needed |
|
100% or more |
| Search and locate desired library components using Library Browser |
1. through 3.
| | Click to open Find dialog box; type in entire search string and hit Apply |
| 4. | View listing and expand columns to see hidden information |
|
Two steps:
| 1. |
Type the 1st few characters of the search string directly at the top of the component name or other column |
 |
| 2. | Search begins immediately and columns are automatically resized to fit text |
|
100% or more |
| Setup variables to tune or optimize |
1. and 2., per component:
| | Select each component or VAR item that has variables you want to optimize; then select and edit/enable each variable |
| 3. | Select each component again to change or enable/disable variables |
|
Two steps:
| 1. |
Open the new Simulation Variables Dialog |
 |
| 2. | All simulation variables (including those in subnetworks) may be edited and enabled/disabled for tuning or optimization |
|
100% or more |
| Setup and use Yield Sensitivity Histograms to Design for Manufacturing (DFM) |
1. through 3., per analysis:
| | Setup Yield Specifications and variables on schematic; run yield analysis; configure complex data display expressions to view histograms |
| 4. | Repeat entire process as additional Yield Specifications are added or removed |
|
Three steps:
| 1. |
and 2, per analysis: Setup yield specifications and variables on schematic; run yield analysis |
 |
| 3. | Place Yield Sensitivity Histogram template matching the number of yield specifications onto Data Display and set name of Yield specification(s) – in just a few minutes! |
|
100% or more |
| Measure the swept Power Added Efficiency of an amplifier during part of signal frame |
1. through 3.
| | Add sensing components to bias lines in amplifier circuit; edit parameters on PAE subnetwork; setup variables on PAE subnetwork; (measurement cannot be gated to signal frame) |
| 4. | Display and interpret results to find desired S-parameters. |
|
Two steps:
| 1. |
Connect new PAE Test Bench to amplifier signal and power ports; set signal frame segments to be measured – saves hours of setup; now just a few minutes! |
 |
| 2. | Run simulation to obtain swept PAE measurements |
|
200% or more |
† Representative single example; average transient speed-up for circuits > 10,000 nodes is 6X
†† Using new multi-threaded matrix load |
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