Agilent Technologies PCI Express* Technology Backgrounder
June 16, 2011
PCI Express* (PCIe*) technology is a standard developed by the PCI-SIG® (PCI Special Interest Group) that is used in various industries, including aerospace industry, wireline and wireless communications vendors, the embedded market and the computing sector, switch manufacturers and HBA (Host Bus Adapters) vendors. PCIe devices can take several forms including an integrated circuit attached to a motherboard or an expansion card fitting into a socket, existing PCI Express devices includes network cards, disk controllers, chipsets, personal computers, switches and add-in cards such as video and graphics.
The PCIe standard is a serial technology which addresses shortcomings and replaces legacy parallel PCI and PCI-X busses. Both PCIe 1.0a and PCIe 1.1 technologies are multilane 2.5GT/s (giga transfers per second) serial interfaces. The PCIe 2.0 specification doubles that performance to 5.0GT/s; and the PCIe 3.0 standard running at 8 GT/s once again doubling the data throughput through changes in the encoding scheme.
The PCIe specification addresses the business and technical demands facing the developers and designers who design products according to this standard to ensure interoperability between two PCIe devices. The business needs include reducing development costs, shortening time to market, protecting investments as data rate or link width measurements increase, and guaranteeing product compliance. As for technical demands, PCIe technology can rapidly identify protocol validations, conduct faster validation of device performance and meet specification compliance.
Agilent Technologies, which has a history of offering tools from the physical layer through the data link layer to the transaction layer, has been dedicated to the advancement of PCI-SIG technologies since the early 1990s. According to Rick Eads, PCI Express program manager of Agilent's Digital Test Division, who also serves as a director on the PCI-SIG Board. "Agilent offers a complete portfolio of PCIe 3.0 test solutions to our customers, resulting in greater productivity to deliver quality products while meeting time-to-market demands."
Evolution of PCI Express
Established in 1992, PCI-SIG is the organization that developed and currently manages the PCI and PCI Express bus standards designed for high-performance input/output (I/O) interconnect to transfer data between a CPU and its peripherals. The industry body, comprised of more than 900 leading companies, is responsible for supporting new testing requirements, preserving backward compatibility, contributing to the technical longevity of I/O technologies and adapting them to the needs of the market.
In 2007, PCIe 2.0 doubled the PCIe data rate from 2.5GT/s to 5GT/s, meaning an x32 connector can transfer data at up to 16GT/s in each direction. The higher bandwidth makes it possible for developers and designers to implement narrower interconnects, increase productivity and decrease costs.
Furthermore, PCIe 3.0 is backward compatible with PCIe 2.0, 1.1 and 1.0a, which allows devices and motherboards designed for generation 3.0 to work with the prior standards. The standard has improved the point-to-point data transfer protocol and its software architecture, and it has become more tolerant of jitter and probe testing.
Figure 1: PCI Express 3.0 Design and Verification Tasks and Examples per Layer
PCI Express 3.0 Verification
PCIe 3.0 verification generally begins from the physical layer to the data link and ends at the transaction layer. The measurements along the physical layer ensure basic parameters such as frequency and voltage swings are met, so that two PCIe devices can communicate with each other. Other elaborate measurements such as jitter analysis or jitter tolerance enable the two devices to reliably transfer bits and bytes over a longer period of time.
The second step of verification focuses on ensuring data packets are transferred correctly on the bus and that any data that is corrupted – such as traffic generation and error insertion, can be recovered. The final stage addresses the transaction layer in which two devices exchange the appropriate communication packets to meet the application needs. Transaction layer testing includes performance, ensuring that the bus meets the maximum bus bandwidth and minimal latency, as well as functional, ensuring that the transaction layer can appropriately handle any errors that may occur.
Agilent Technologies' PCIe 3.0 Test Portfolio
Agilent covers the full design cycle, from research and development to QA, validation and compliance testing of components and boards, providing customers with tools that are needed to conduct reliable, faster and easier testing and compliance testing of PCIe 3.0 devices. Unlike competitors, Agilent's PCIe 3.0 tools also make it possible for developers and design and test engineers to support PCIe 2.0, 1.0a and PCIe 1.1 devices, identify protocol violations and debug failure issues.
Agilent offers tools that correspond to the application's specific requirements – pattern/noise generators to stress test receivers and transceivers with patterns and pulses; real-time and sampling oscilloscopes to verify signal integrity; BERTs to test jitter tolerance; and protocol analyzers to acquire insight into data link and transaction layers including Link Training and Status State Machine (LTSSM) support for traffic generation, protocol layer validation, as well as performance testing.
The PCIe 3.0 portfolio of products includes:
Agilent's Digital Test Console, the industry's only complete and integrated x1 through x16 protocol analyzer and exerciser solution for PCI Express 3.0 specification. The transition to PCIe 3.0 will be a challenge for many test engineers and validation labs, with such high speeds and maintain the same electrical channel requirements; a complete change in the encoding scheme; and many advanced protocol features. Agilent's PCIe test system addresses these challenges associated with the transition to PCI Express 3.0. Introducing industry's only equalization snoop probe (ESP) technology for reliable data capture at 8 GT/s; LTSSM Tester to exerciser and validate new encoding and protocol state machine designs; and a flexible GUI to help debug advanced protocol features.
Infiniium 90000X Series Oscilloscopes – provides 16 GHz to 32 GHz bandwidth with up to 80 GSa/s sample rate and up to 2G acquisition memory; the industry's lowest noise and jitter measurement floor and selection of software packages. For PCI Express technology, the 90000X's deep memory easily exceeds the requirement to capture a minimum of 1 million unit intervals of waveform data for jitter and voltage margin analysis. Agilent also offers a turnkey compliance package called the N5393C PCI Express Electrical Compliance package. Combined with the low noise floor of the Infiniium 90000X-series oscilloscopes, the N5393C provides the accuracy you need for maximizing performance of PCIe 3.0 devices. The N5393C provides measurements for uncorrelated TJ, uncorrelated DJ, uncorrelated PWJ, voltage preshoot and de-emphasis measurements, and supports the de-embedding of test fixtures with the optional Agilent N5465A InfiiniSim Waveform Transformation Toolset.The N5393C also support PCIe 2.0 and 1.1/1.0a measurements and reference clock analysis providing results consistent with the PCI-SIG's own SIGtest utility for PCIe Express measurements.
J-BERT N4903B High-Performance Serial BERT with Complete Jitter Tolerance – allows characterization of jitter tolerance of the devices' input; it checks compliance by emulating compliant stress conditions, such as PCIe 3.0 compliant random jitter, dual-tone periodic jitter, ISI, sinusoidal interference, SSC and residual SSC, and common-mode and differential mode interference For signal analysis, it has built in fast total jitter measurements, BERT Scan, eye mask tests and eye analysis tools to evaluate the PCIe 3.0 design.
81150A Series Pulse Function Arbitrary Noise Generator – provides repeatable and random noise for the receiver compliance tests with a selectable crest factor up to 7. The instrument can provide random jitter as well as deterministic jitter needed for the compliance test. The noise can be added to a pattern generator via delay line.
E2960B Protocol Analyzer and Exerciser for PCIe 2.0 technology – A validation and verification solution for PCIe 2.0 protocol testing. The exerciser makes it possible to validate key parts of the PCIe 2.0 design, include Link Training and Status State Machine (LTSSM), Link and Transaction Layer, Power management states, as well as performance validation. The protocol analyzer tools in the E2960B family help debug interoperability issues. With a protocol to logic (P2L) gateway cable, it provides correlation to other buses on logic analyzers, e.g. correlated PCIe 2.0 and DDR 2.0 debugging. This gives digital designers a full system view of their design, and makes debugging easier.
N5323A Jammer - Industry's first PCI Express® (PCIe) Inline Error Injector tool –
The Jammer provides unprecedented ability to test PCIe 2.0 devices or software drivers in live systems, regardless of operating system and application type. In a typical setup, the Jammer sits transparently between two devices, and can be programmed to modify real PCIe data transfers on the fly, to create disruption test scenarios. Almost any conceivable error recover tests cases can be programmed. This new capability allows developers and test engineers to improve error handling, and avoid costly late product changes or product recalls..
E2969B Protocol Test Card (PTC) II – Approved by the PCI-SIG for protocol "Gold" testing, helps validate the compliance of designs to the PCIe 2.0 specification. It is also expandable to the Agilent compliance assured test package with an additional 180 test cases to simplify protocol validation.
W2212 Advanced Design System (ADS) Core, Transient Convolution, Layout, Momentum G2, EMDS, Ptolemy Bundled – PCIe engineers who are hurdling the multi-gigabit/s barrier look to ADS for the correct treatment of high-speed effects like distortion, mismatch, and crosstalk. Uniquely, ADS integrates accurate system, circuit, and EM simulators, so you can not only get the right answers but also get them faster by avoiding error-prone and time-consuming data transfer between a collection of point tools.
Figure 2: The Agilent Design and Test Portfolio for PCIe 3.0
*PCI-SIG, PCI Express and PCIe are trademarks or registered trademarks of PCI-SIG.
Agilent's Digital Test Standards Program
Agilent's measurement solutions and services development for digital applications is driven and supported by the work that Agilent's experts do in the various international standard committees. The Agilent Standards Program for digital applications comprises Double Data Rate (DDR) memory, PCI Express®, DisplayPort, Universal Serial Bus (USB), Serial ATA (SATA), Serial Attached SCSI (T10), High-Definition Multimedia Interface (HDMI®), DigRF and optical transceiver test. Our experts are in the Board of Directors in Joint Electronic Devices Engineering Council (JEDEC), PCI-SIG® and Video Electronics Standards Association (VESA). Agilent is a contributing member in Serial ATA International Organization (SATA-IO), USB-Implementers Forum (USB-IF) and Mobile Industry Processor Interface (MIPI) Alliance.
Agilent's involvement in these standards gives Agilent and its customers, the computing and communication component vendors to the electronics consumer market, two main advantages:
- First, it enables us to bring the right products to the market when our customers need them. We aim to be first to market with our solutions so you as our customer can be first to market with your products ensuring standard compliance.
- Second, with Agilent's involvement in plug-fests, workshops and seminars we are in the unique position to develop solutions that evolve with the standards, giving you the ability to design the best products with the highest confidence.
PCI Express, PCIe and PCI-SIG are registered trademarks and trademarks respectively of the PCI-SIG.
HDMI, the HDMI logo and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC.
Agilent Technologies to Showcase PCI Express® 3.0 Test Solutions at IDF2010
|Press Release:||Agilent Technologies Introduces Industry-First Flying Leads Probe for Embedded PCI Express(r) 2.0 Design, Validation
Additional information about Agilent's PCIe solutions at: www.agilent.com/find/pciexpress
Additional information about PCIe 2.0 solutions at: www.agilent.com/find/pciexpress2
Additional information about PCI-SIG technologies can be found at: www.pcisig.com
Janet Smith, Americas
Sarah Calnan, Europe
Iris Ng, Asia